Digital Timing Basics for VLSI Interview & SoC Design
What you’ll learn
Basics of Flop & Latch Timings
Set-up, Hold, Clock to Q, Clock Skew
Set-up & Hold violation checks
Set-up & Hold violation fixes
Latency Minimization
Set-up & Hold Margin in Digital Ckts
Min & Max Path Analysis
Clock Gating
F-V Curve in SoC
Requirements
Knowledge of Flop functionality will suffice
Description
A VLSI Course on Basic Timing Checks for Digital Logics – A MUST Course for VLSI students and professionals intended to work in Physical Design / Front-end (RTL) Design / Verification / Circuit Design.Understanding of Flop, Latch and Logic Gates timings (Set-up time, hold-time, Clock to Q delay) is very crucial for every VLSI designer. Whether you are working as Physical Designer (back-end) or RTL designer (front-end) or Verification engineer or Circuit Designer, Digital logics and associated timings form the basis of design performance in SoC design.Clock skew is another important factor in Static Timing Analysis. This course will cover most critical timing aspects of Flops and how set-up and hold margins are computed in Digital design. In addition, this course will provide insights to latency minimization, another crucial aspect of Physical Design.This is a MUST Course for every VLSI aspirants who aspire for a successful career in semiconductor industry. If you are preparing for VLSI interview or GATE exam, then this is right course for you.All the concepts taught in this lecture series are followed by relevant examples which will help students to get a full understanding of each concept. This is perfect course for VLSI interview preparation.This Crash Course is prepared by VLSI industry expert with inputs from Industry professionals working in companies such as Texas Instruments, AMD, Intel, Qualcomm, Rambus, Samsung etc.Concepts covered in this course are – Flop and Latch operation, Set-up time, Hold time, Clock to Q delay, Buffer, Clock Skew, Set-up Margin, Hold Margin, Cycle path analysis, Digital vs Physical implementation, Example of violations and fixing those violations, Latency minimization, Clock-Gating and Frequency-Voltage Curve in SoC.All the best for your VLSI journey!
Overview
Section 1: Introduction
Lecture 1 Introduction
Section 2: Understanding Flop Timings
Lecture 2 Basic Definitions
Lecture 3 Quick Summary
Lecture 4 Set-up Time & Set-up Margin
Lecture 5 Hold time & Hold Margin
Lecture 6 Clock to Q Delay
Section 3: Static Timing Foundation
Lecture 7 Buffer
Lecture 8 Logic Implementation
Lecture 9 Physical Implementation
Lecture 10 Set-up Time Condition in Cycle Path
Lecture 11 Hold Time Condition in Cycle Path
Lecture 12 Example for Set-up & Hold Condition
Section 4: Problem Solving for Interview
Lecture 13 Set-up & Hold Margin Computation
Lecture 14 Set-up Violation
Lecture 15 Set-up Violation Fix : Clock Path Delay
Lecture 16 Hold Violation
Lecture 17 Hold Violation Fix: Data Path Delay
Lecture 18 Good Margin but Higher Latency
Lecture 19 Latency Reduction with Optimized Design
Lecture 20 Design Issues in Real World SoC
Section 5: Advanced Concepts for Interview- Timing Margins
Lecture 21 Positive Latch – Setup & Hold Time
Lecture 22 Negative Latch – Set-up & Hold Time
Lecture 23 Clock Gating – Set-up & Hold Time
Lecture 24 Negative Hold Time for Flop
Lecture 25 Negative Set-up Time for Flop
Section 6: Common Misconceptions
Lecture 26 Set-up, Hold, Clk2Q and Clock Skew
Lecture 27 Hold Margin with Frequency
Lecture 28 Set-up Margin with Frequency
Section 7: Frequency vs Voltage in SoC
Lecture 29 F-V Curve : Introduction
Lecture 30 F-V Curve: Explanation
Section 8: Practical Design Issue-1: Multiple Parallel Paths
Lecture 31 Multiple Path – Problem Statement
Lecture 32 Multiple Path – Set-up Time Analysis
Lecture 33 Multiple Path – Hold Time Analysis
Lecture 34 Multiple Path – Summary
Section 9: Practical Design Issue -2 : Max & Min Frequency of Operation
Lecture 35 Frequency of Operation
Lecture 36 Minimum Frequency of Operation
Lecture 37 Maximum Frequency of Operation without Clock Skew
Lecture 38 Maximum Frequency of Operation with Clock Skew
Section 10: Quiz & Next Step
Lecture 39 Next Step
VLSI students,VLSI professionals,Electronics Engineer,Electrical Engineer,Physical Design Engineer,RTL Designer,Circuit Designer,Verification Engineer,SoC Designer
Course Information:
Udemy | English | 4h 1m | 1.11 GB
Created by: Learnin28days Academy
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