Function Acceleration on FPGA with VitisPart 1 Fundamental

Embedded System Accelerators with Vitis and HLS
Function Acceleration on FPGA with VitisPart 1 Fundamental
File Size :
6.66 GB
Total length :
9h 26m

Category

Instructor

Mohammad Hosseinbady

Language

Last update

10/2021

Ratings

4.5/5

Function Acceleration on FPGA with VitisPart 1 Fundamental

What you’ll learn

Understanding the basic concepts of FPGA-Based embedded systems
Understanding the Xilinx Zynq 7000 SoC and Zynq UltraScale+ MPSoC architectures
Accelerating functions in the Xilinx Vitis unified software platform
Using C/C++/OpenCL for accelerating compute-intensive algorithms on Zynq platforms
Running the accelerated applications on software and hardware emulators
Running the accelerated applications on actual FPGAs
Working with Zybo-Z7-20 and Ultra96V2 Zynq-based FPGA platforms
Implementing three exciting projects with Vitis

Function Acceleration on FPGA with VitisPart 1 Fundamental

Requirements

Understanding the basic concepts of C/C++ coding
Xilinx Vitis software unified platform
A Zynq-Based FPGA such as Zybo-Z7-20 or Ultra96v2

Description

This course is an introduction to function acceleration in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing compute-intensive algorithms on FPGA-based embedded systems using C/C++ language without any help from HDLs (e.g., VHDL or Verilog).The course introduces the Xilinx Zynq embedded systems and then explains how to use Xilinx toolsets to map applications on them.It uses the Xilinx Vitis unified software platform to describe real examples and applications for embedded systems. The course follows the software and hardware emulation schemes as well as running the applications on the actual FPGAs.Each section of the course uses several examples, quizzes and exercises to explain complex designing concepts easily and smoothly.Along the course, you will work with several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises two exciting projects to put all the explained concepts together to design real circuits and hardware controllers.This course is the first of a series of courses on function acceleration on Zynq-based embedded systems. Whereas this course focuses on fundamental concepts, the other courses will explain different optimisation techniques in Vitis.

Overview

Section 1: Prologue

Lecture 1 Introduction

Lecture 2 Course Structure

Section 2: Embedded Systems

Lecture 3 Introduction

Lecture 4 Definition

Lecture 5 FPGA Role

Lecture 6 HLS Role

Lecture 7 Zynq

Lecture 8 Zynq MPSoC

Lecture 9 Exercises

Section 3: LAB Structure

Lecture 10 Introduction

Lecture 11 Definition

Lecture 12 Design Flow

Lecture 13 Exercises

Section 4: Hardware/Software Setup

Lecture 14 Introduction

Lecture 15 Setup Structure

Lecture 16 VirtualBox

Lecture 17 Xilinx Vitis

Lecture 18 ZCU102 Board — Vitis Platform

Lecture 19 Ultra96v2 Board — Vitis Platform

Lecture 20 ZyboZ7-20 Board — Vitis Platform

Section 5: Vitis-DesignFlow

Lecture 21 Introduction

Lecture 22 Definition

Lecture 23 Vitis Project

Lecture 24 Software Emulation

Lecture 25 Hardware Emulation

Lecture 26 Actual FPGA Hardware

Lecture 27 Exercises

Section 6: Host Program

Lecture 28 Introduction

Lecture 29 Programming Model

Lecture 30 OpenCL Concepts

Lecture 31 Host Structure

Lecture 32 Host Code

Lecture 33 Exercises

Section 7: Scaling Example

Lecture 34 Introduction

Lecture 35 Definition

Lecture 36 Kernel Execution Model

Lecture 37 Kernel Code

Lecture 38 Burst Data Transfer

Lecture 39 Host Code

Lecture 40 Lab: Executing

Lecture 41 Lab: Debugging

Lecture 42 Exercises

Section 8: Image Thresholding Example

Lecture 43 Introduction

Lecture 44 Definition

Lecture 45 Kernel Code

Lecture 46 Host Code

Lecture 47 Emulation — Lab

Lecture 48 Hardware — Lab

Lecture 49 Exercises

Section 9: Linear Relationship Accelerator Example

Lecture 50 Introduction

Lecture 51 Definition

Lecture 52 Kernel Code

Lecture 53 Host

Lecture 54 Lab — Emulator

Lecture 55 Lab — Hardware

Lecture 56 Exercises

Section 10: Loop Optimisation

Lecture 57 Introduction

Lecture 58 Definition

Lecture 59 Loop Latency

Lecture 60 Loop Unrolling

Lecture 61 Array Partitioning

Lecture 62 Loop Merge

Lecture 63 Loop Pipeline

Lecture 64 Nested Loops: Flattening

Lecture 65 Data Dependencies

Lecture 66 Memory Dependencies

Lecture 67 Exercises

Section 11: Matrix-Vector Multiplication (mxv)

Lecture 68 Introduction

Lecture 69 Definition

Lecture 70 Kernel Access Pattern

Lecture 71 Kernel Loops

Lecture 72 Lab

Lecture 73 Exercises

Section 12: Hardware/Software Partitioning

Lecture 74 Introduction

Lecture 75 Definition

Lecture 76 Gperftools

Lecture 77 Gperftools Lab

Lecture 78 Exercises

Section 13: Project 1: Sparse Matrix-Vector Multiplication (SpMV)

Lecture 79 Introduction

Lecture 80 Definition

Lecture 81 Baseline Code LAB

Lecture 82 HLS Code – 01

Lecture 83 HLS Code – 01 Lab

Lecture 84 HLS Code – 02

Lecture 85 HLS Code – 02 Lab

Lecture 86 Vitis Lab

Section 14: Project 2: Support Vector Machine (svm)

Lecture 87 Definition

Lecture 88 Software Code

Lecture 89 Code Structure

Lecture 90 HLS Code

Lecture 91 Lab

Section 15: Appendix

Lecture 92 How to create zybo-z7-20 Hardware Vitis 2020.2 Platform

Lecture 93 Vitis 2021.1 Embedded Platform for Zybo-Z7-20

Hardware engineers,Software engineers who are interested in FPGA,Lecturers, researchers, professors who want to use FPGA-based embedded systems in lectures, courses or research

Course Information:

Udemy | English | 9h 26m | 6.66 GB
Created by: Mohammad Hosseinbady

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