HighLevel Synthesis for FPGA Part 2 Sequential Circuits

Logic Design with Vitis-HLS
HighLevel Synthesis for FPGA Part 2 Sequential Circuits
File Size :
7.80 GB
Total length :
9h 28m

Category

Instructor

Mohammad Hosseinbady

Language

Last update

3/2023

Ratings

4.5/5

HighLevel Synthesis for FPGA Part 2 Sequential Circuits

What you’ll learn

Designing sequential logic circuits with C/C++ language using the HLS approach
Understanding the basic concepts of High-Level Synthesis (HLS)
Using HLS concepts for designing sequential logic circuits
HLS design flow for FPGAs
Working with Xilinx Vitis-HLS and Vivado design suite Toolsets
How to generate RTL hardware IPs using Vitis-HLS
Writing C-testbench in HLS
Implementing three exciting projects with HLS

HighLevel Synthesis for FPGA Part 2 Sequential Circuits

Requirements

Understanding the basic concepts of C/C++ coding
“High-Level Synthesis for FPGA, Part 1 – Combinational Circuits” course
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado toolsets

Description

This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

Overview

Section 1: Prologue

Lecture 1 Introduction

Lecture 2 Course Structure

Section 2: HW/SW Setup

Lecture 3 Introduction

Lecture 4 Vivado-HLX

Lecture 5 Vivado and Vitis-HLS

Lecture 6 Install Vivado HLx

Lecture 7 Test Installation

Section 3: D Flip-Flop (DFF)

Lecture 8 Introduction

Lecture 9 Memory Cell

Lecture 10 Sequential Circuits

Lecture 11 Clock Signal

Lecture 12 State Concept

Lecture 13 Reset Signal

Lecture 14 Register

Lecture 15 DFF LAB01

Lecture 16 DFF LAB02

Lecture 17 Exercises

Section 4: Single Cycle Design Flow

Lecture 18 Introduction

Lecture 19 Definition and Idea

Lecture 20 Parallel to Serial

Lecture 21 Serial to Parallel

Lecture 22 IP-Centric Design Flow

Lecture 23 Parallel-Serial-Parallel LAB

Lecture 24 Exercises

Section 5: Testbench 01

Lecture 25 Introduction

Lecture 26 Definition

Lecture 27 Parallel to Serial Testbench

Lecture 28 Serial to Parallel Testbench

Lecture 29 Input Waveform

Lecture 30 Exercises

Section 6: State Machine

Lecture 31 Introduction

Lecture 32 Definition

Lecture 33 Concepts

Lecture 34 Template

Lecture 35 Combination Lock-VitisHLS

Lecture 36 CombinationLock-Vivado

Lecture 37 Exercises

Section 7: Utilities

Lecture 38 Introduction

Lecture 39 Timer

Lecture 40 Debouncer

Lecture 41 Counter

Lecture 42 Clock Generator

Lecture 43 Pulse Generator

Lecture 44 Single-Cycle Regular Pulses

Lecture 45 Edge Detector

Lecture 46 Exercises

Section 8: Vending Machine

Lecture 47 Introduction

Lecture 48 Definition

Lecture 49 Vitis-HLS

Lecture 50 Vivado

Lecture 51 Exercises

Section 9: Integrated Logic Analyzer (ILA)

Lecture 52 Introduction

Lecture 53 Definition

Lecture 54 Vivado

Lecture 55 Exercises

Section 10: Function Pipelining

Lecture 56 Introduction

Lecture 57 Definition

Lecture 58 Multi-Cycle Design

Lecture 59 Pipeline Design

Lecture 60 Performance Metrics

Lecture 61 IIR Example

Lecture 62 Exercises

Section 11: Seven Segments

Lecture 63 Introduction

Lecture 64 Definition

Lecture 65 7Segment Driver

Lecture 66 7Segment HLS

Lecture 67 7Segment Vivado

Lecture 68 Four-Digit Counter

Lecture 69 Exercises

Section 12: PMOD

Lecture 70 Introduction

Lecture 71 Definition

Lecture 72 PMOD LED

Lecture 73 PMOD Keyboard

Lecture 74 Exercises

Section 13: Interface Synthesis

Lecture 75 Introduction

Lecture 76 SCII Proc&Cons

Lecture 77 Definition

Lecture 78 Interface Synthesis

Lecture 79 Block Level ap_ctrl_hs

Lecture 80 Block Level ap_ctrl_hs: vitis-hls

Lecture 81 Port Level ap_vld

Lecture 82 Port Level ap_ack

Lecture 83 Port Level ap_hs

Lecture 84 Exercises

Section 14: Project 1: Digital Dice

Lecture 85 Introduction

Lecture 86 Definition

Lecture 87 Counter Based

Lecture 88 LFSR

Lecture 89 Exercises

Section 15: Project 2: UART

Lecture 90 Introduction

Lecture 91 Definition

Lecture 92 Design Structure and HLS

Lecture 93 Transmitter-VitisHLS+Vivado

Lecture 94 Receiver-VitisHLS+Vivado

Lecture 95 Exercises

Section 16: Project 3: Stepper Motor

Lecture 96 Introduction

Lecture 97 Definition

Lecture 98 One-Phase-On: Vitis-HLS

Lecture 99 Two-Phase-On: Vitis-HLS

Lecture 100 Two-Phase-On with Control: Vitis-HLS

Lecture 101 One&Two-Phase-On (Half Step): Vitis-HLS

Lecture 102 Exercises

Hardware engineers,Software engineers who are interested in FPGA,Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research,Digital Logic enthusiasts

Course Information:

Udemy | English | 9h 28m | 7.80 GB
Created by: Mohammad Hosseinbady

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