Learn FPGA Design With VHDL IntelAltera
What you’ll learn
We will cover the VHDL language and syntax with lots of example projects
Relate VHDL code to hardware implementation
Creating FPGA building blocks using VHDL
Creating State Machines using VHDL
Creating complex FPGA designs from scratch
Highlight good design practice & common pitfalls
Writing Test Benches in VHDL
Simulate & debug FPGA Designs using ModelSim
Use the Intel Quartus software to compile and implement projects
Use Quartus To Perform Pin Assignments
Programming FPGAs using the USB Blaster
Using the Quartus Netlist Viewer to view the Hardware Realisation
Making sense of the Quartus Fitter Reports
Quartus Assignment Editor
Quartus Settings, Options & Optimisations
Basic Introduction to Quartus Timing Analyser
Implement a UART project that communicates over RS232 with a PC
Implement a State Machine project
Implement a 4 Digit 7-Segment Display to print a Count value
Implement a Project to Create A PWM output
Implement a Shift Register to Drive LEDs
Implement a Project to cover Switch De-bouncing and Synchronisation
Requirements
Fundamentals of digital electronics & logic gates
Knowledge of binary and hexadecimal number systems
Description
Course Audience :This course is aimed at students & engineers who want to get into the field of FPGA development using VHDL. No prior knowledge in VHDL/FPGA is assumed so we will start from the very basics. Students should have a basic knowledge of digital electronics including logic gates and flip-flops.Course Summary :This course covers the VHDL language in detail. In between lectures, we will complete a number of fun projects (please see below) with increasing complexity to consolidate the knowledge we have gained during the course. We will go through how to write Test Benches and we will implement a number of Test Benches to verify the UART project. We cover the Intel Quartus software in detail and also go through how to simulate Test Benches using using ModelSim.Projects (Implemented and Tested On a Cyclone IV Development Board):1. Reading a switch input and driving an LED output2. Simple State Machine which reacts to user input and drives a number of LEDs3. Synchronising and de-bouncing a Switch Input.4. Generating a PWM output.5. Designing a Shift Register.6. 4 Digit 7-Segment display for counting the number of push button activations7. UART module & State machine for echoing back characters received from a PC over RS232Intel Quartus Softare:1. Creating & Compiling a new project 2. Performing pin assignments.3. Basic introduction to Quartus IP Catalogue.4. Using the USB Blaster to program the FPGA via JTAG.5. Using the Quartus Net List Viewer to explore the hardware realisation of your design.6. Making sense of Quartus Fitter Reports to better understand resource allocation.7. Using the Quartus Assignment Editor.8. Overview of Quartus settings, options and optimisations.9. Basic introduction to timing analyser, timing constraints and SDC files.Intel ModelSim Starter Edition Software :1. Creating a new ModelSim Project.2. Writing & compiling Test Benches.3. Running simulations.4. Using the Waveform viewer to analyse results.Course Details :We will start by covering the basics of FPGA hardware. This hardware background is vital and as we learn how to write VHDL, we will also refer back to how our code gets implemented in hardware. In the second section of the course, we will cover the VHDL language in detail. We will cover all the aspects (Signals & Data types, VHDL Keywords & Operators, Concurrent & Sequential statements, Entity & Architecture, Process Block, Generics, Constants & Variables, Records, Component Instantiation, Procedures & Functions, Packages & Libraries and Type Conversions) that are needed to be able to develop complex and advanced FPGA designs. There will be plenty of simple examples to allow you to learn the VHDL language quickly and enable you to confidently write your own code. We will also look at how most of the VHDL language maps to hardware on the actual device.With this strong foundation in the language, we will look at how to build fundamental FPGA blocks starting from Tri-State Drivers, Registers, Comparators, Multiplexers, Shift Registers, Serialisers, RAMs & ROMs and Finite State Machines. We will look at how to code all of the above structures and also explore how these are implemented in real hardware in the FPGA.In the next section, we will look at hierarchical design with VHDL. This design practise is used when creating complex designs having more than one design unit. We will explore this concept from an example to see how design units can be joined together to form a hierarchical design.In the next section we will explore good FPGA design practise. From my experience most beginners in FPGA design make common mistakes and fall into certain traps. Some of these can lead to issues that are very difficult to debug and fix. The idea behind this section is to make you aware of these common pitfalls and explore ways in which we can circumvent these. We will talk about Latches, Generated Clocks, Clock & Data Gating, Benefits of a Register Rich Design, Benefits of Synchronous Design, Dealing With Asynchronous Inputs, Clock Domain Crossing, Designing for Reuse, Signal Initialisation, Synchronising Reset De-assertion, Routing Clocks & Resets and Using PLLs.By this stage, we would have covered a lot of the theory and also completed a number of design projects so you should have the knowledge to create your own FPGA designs independently. We will now cover design verification. This section will explore how to write test benches. We will explore aspects of VHDL coding styles for writing test benches. We will discuss how to perform file IO for creating input vectors and to store output results. We will also discuss self-checking test benches to help automate the test process.In the final section of the course, we will design a UART module controlled by a State machine. We will write VHDL code to implement the UART and state machine from scratch. We will use a hierarchical design approach where we will have a number of design units. We will write test benches for each design unit and perform simulations (using ModelSim) for verification. We will bring all design units together into our top level VHDL module and do a system level simulation. Next, we will explore how to create & configure a project in Intel Quartus to implement our design on our FPGA development board. We will look at how to do the pin assignments and also very briefly look at applying very basic timing constraints to get our design to pass. We will then test the design on real hardware to make sure our design works as intended.
Overview
Section 1: Course Videos
Lecture 1 Introduction
Lecture 2 Cyclone IV Development Board
Lecture 3 Installing Quartus
Lecture 4 FPGA Fundamentals
Lecture 5 Signals & Data Types I
Lecture 6 Signals & Data Types II
Lecture 7 Constants
Lecture 8 VHDL Operators
Lecture 9 Structure of a VHDL File
Lecture 10 Project : Switch And LED
Lecture 11 The Process Block
Lecture 12 State Machine Project
Lecture 13 Component Instantiation
Lecture 14 Project : Using Quartus IP Wizard To Generate PLL
Lecture 15 Quartus Netlist Viewer & Fitter Reports
Lecture 16 Quartus Settings & Options
Lecture 17 VHDL Concurrent Statements
Lecture 18 VHDL Sequential Statements
Lecture 19 Signal Assignments I
Lecture 20 Signal Assignments II
Lecture 21 How To Generate A PWM
Lecture 22 Project : PWM LED
Lecture 23 Variables
Lecture 24 Functions and Procedures
Lecture 25 Packages and Libraries
Lecture 26 Parameterised Components
Lecture 27 Type Conversions
Lecture 28 Miscellaneous Topics
Lecture 29 Tri-State Drivers
Lecture 30 Comparators
Lecture 31 Multiplexers
Lecture 32 Shift Registers
Lecture 33 Serialisers
Lecture 34 RAMs & ROMs
Lecture 35 Finite State Machines
Lecture 36 Good Design Practice I
Lecture 37 Good Design Practice II
Lecture 38 Project : LED Shift Register
Lecture 39 How To Debounce A Switch Input
Lecture 40 Project : De-bouncing Asynchronous Input
Lecture 41 Quartus Timing Analyser
Lecture 42 Driving A Seven Segment Display
Lecture 43 Project : 4 Digit Counter Using Seven Segment Display
Lecture 44 Test Benches I
Lecture 45 Test Benches II
Lecture 46 Test Benches III
Lecture 47 UART Block Diagram
Lecture 48 RS232 Protocol
Lecture 49 BaudClkGenerator Block Diagram
Lecture 50 BaudClkGenerator VHDL
Lecture 51 BaudClkGenerator Test Bench
Lecture 52 Serialiser Block Diagram
Lecture 53 Serialiser VHDL
Lecture 54 Serialiser Test Bench
Lecture 55 UART Transmitter VHDL
Lecture 56 UART Transmitter Test Bench
Lecture 57 Shift Register VHDL
Lecture 58 Shift Register Test Bench
Lecture 59 Synchroniser VHDL
Lecture 60 Synchroniser Test Bench
Lecture 61 UART Receiver VHDL
Lecture 62 UART Receiver Test Bench
Lecture 63 Summary So Far
Lecture 64 Top Level Module VHDL
Lecture 65 Top Level Module Test Bench I
Lecture 66 Top Level Module Test Bench II
Lecture 67 Quartus Implementation
Lecture 68 Conclusion
Lecture 69 Quartus Project
Graduate students looking for a career as an RTL engineer or Design Engineer,Electronics engineers/hobbyists who want to get into the field of FPGA design,Those interested in FPGA development who are looking for an introductory course,Anyone about to embark on their first VHDL design project
Course Information:
Udemy | English | 20h 14m | 8.93 GB
Created by: Lakshman Athukorala
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