Learn VHDL and FPGA Development

Learn how to create a VHDL design that can be simulated and implemented on a Xilinx or Altera FPGA development board.
Learn VHDL and FPGA Development
File Size :
4.21 GB
Total length :
13h 24m

Category

Instructor

Jordan Christman

Language

Last update

Last updated 10/2022

Ratings

4.7/5

Learn VHDL and FPGA Development

What you’ll learn

Understand the design process for implementing a digital design onto a FPGA
Learn how to simulate a design in Altera’s ModelSim and Xilinx Isim
Learn how to use Xilinx ISE tool to program FPGA
Debug a VHDL design using ModelSim
Simulate a VHDL design using ModelSim
Familiarize yourself with Altera and Xilinx tools
Program a FPGA

Learn VHDL and FPGA Development

Requirements

Purchase a BASYS 3 or BASYS 2 FPGA Development Board
Download Xilinx ISE webpack if your using the BASYS 2, but we will cover that in this course!
Download Vivado if your using the BASYS 3 board, we will cover this in the course!
Basic understanding of Binary Notation
Basic understanding of Hexadecimal Notation
Basic understanding of Logic Gates

Description

This course supports both the Xilinx and Altera FPGA development boards.
VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera’s tools so students are not limited to Xilinx development boards.
Course Structure:
This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.
This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.
Please message me before you sign up for this course!

Overview

Section 1: Contact Information

Lecture 1 Contact Information

Lecture 2 Extra Resources for Using FPGAs

Section 2: Introduction

Lecture 3 Introduction to the Course

Lecture 4 Introduction to VHDL

Section 3: VHDL Data Types

Lecture 5 Data Types Introduction

Lecture 6 Signals / Variables / Constants

Lecture 7 Unsigned / Signed Data Types

Lecture 8 Standard Logic Vector / Standard Logic

Lecture 9 Integer / Boolean Data Types

Lecture 10 Initializing Values in VHDL

Lecture 11 Data Type Examples in VHDL Designs Part 1

Lecture 12 Data Type Examples in VHDL Designs Part 2

Section 4: VHDL Syntax

Lecture 13 VHDL Syntax Introduction

Lecture 14 If Statement / Case Statement

Lecture 15 For Loop / While Loop

Lecture 16 VHDL For Loop Example

Lecture 17 When Else Statement With Select When Statement

Lecture 18 VHDL Processes and Concurrent Statement

Lecture 19 VHDL Syntax Design Example

Section 5: VHDL Coding Structure

Lecture 20 Organizing Your VHDL Designs

Lecture 21 VHDL Design Structure

Lecture 22 VHDL Design Architecture Styles

Lecture 23 Data Flow Architecture Example – Full Adder

Lecture 24 Behavioral Architecture Example – Full Adder

Lecture 25 Concept of VHDL Modeling

Section 6: Test Bench

Lecture 26 Test Benches Introduction

Lecture 27 Test Bench Structure Walkthrough

Lecture 28 Walkthrough of a Completed Test Bench

Section 7: Implementing State Machines in VHDL

Lecture 29 State Machine Introduction

Lecture 30 Designing a State Machine

Section 8: FPGA Development Boards

Lecture 31 Supported FPGA Development Boards

Lecture 32 BASYS 3 Board Overview

Lecture 33 BASYS 3 Board User Guide

Lecture 34 BASYS 3 Board Schematic

Lecture 35 BASYS 2 Board

Lecture 36 BASYS 2 Board User Guide

Lecture 37 BASYS 2 Board Schematic

Lecture 38 BASYS 2 Board Overview

Section 9: Altera Tools

Lecture 39 Altera Tools Introduction

Lecture 40 ModelSim VHDL Simulation Tool

Lecture 41 Quartus II FPGA Development Tool

Section 10: Xilinx Tools

Lecture 42 Xilinx Tools Introduction

Lecture 43 Download the Vivado Tool Suite for the BASYS 3

Lecture 44 ISim VHDL Simulation Tool

Lecture 45 Xilinx ISE FPGA Development Tool

Lecture 46 Programming The BASYS 2 FPGA Development Board

Section 11: Lab 1 – Full Adder

Lecture 47 Introduction

Lecture 48 BASYS 3 Full Adder Demonstration

Lecture 49 BASYS 2 Full Adder Demonstration

Lecture 50 BASYS 2 Full Adder Solution

Section 12: Lab 2 – Shift Register

Lecture 51 Introduction

Lecture 52 BASYS 3 Shift Register Demonstration

Lecture 53 BASYS 2 Shift Register Demonstration

Lecture 54 Shift Register Completed Design

Section 13: Lab 3 – Universal Shift Register

Lecture 55 Introduction

Lecture 56 BASYS 3 Universal Shift Register Demonstration

Lecture 57 BASYS 2 Universal Shift Register Demonstration

Lecture 58 BASYS 2 Universal Shift Register Solution

Lecture 59 Universal Shift Register VHDL Design

Section 14: Lab 4 – 7 Segment Display

Lecture 60 Introduction

Lecture 61 BASYS 3 – 7 Segment Display Demonstration

Lecture 62 BASYS 2 – 7 Segment Display Demonstration

Lecture 63 Hexadecimal to 7 Segment Display VHDL Design

Section 15: Lab 5 – Counter

Lecture 64 Introduction

Lecture 65 BASYS 3 Counter Demonstration

Lecture 66 BASYS 2 Counter Demonstration

Lecture 67 Counter VHDL Design

Section 16: Lab 6 – Multiplier

Lecture 68 Introduction

Lecture 69 BASYS 3 Multiplier Demonstration

Lecture 70 BASYS 2 Multiplier Demonstration

Lecture 71 Multiplier VHDL Design File

Section 17: Lab 7 – RC Servo

Lecture 72 Introduction

Lecture 73 BASYS 3 RC Servo Demonstration

Lecture 74 BASYS 2 RC Servo Demonstration

Lecture 75 RC Servo VHDL Design Files

Section 18: Lecture Notes

Lecture 76 Introduction to VHDL Notes

Lecture 77 Data Types Notes

Lecture 78 Syntax Notes

Lecture 79 Structure Notes

Lecture 80 Coding Styles Notes

Lecture 81 Test Benches Notes

Lecture 82 Altera Tools Notes

Lecture 83 ModelSim Notes

Lecture 84 Quartus II Notes

Lecture 85 Xilinx Tools Notes

Lecture 86 Isim Notes

Lecture 87 Xilinx ISE Project Notes

Lecture 88 Programming BASYS Board

Lecture 89 BASYS 2 Board Notes

Lecture 90 Test Bench Example

Section 19: Extra References

Lecture 91 Free Range VHDL Notes

Lecture 92 VHDL Cookbook

Lecture 93 2

Engineering Students,Engineering Managers,Digital Logic Enthusists,Individuals pursuing Electrical Engineering,Anyone who wants to take it for fun!

Course Information:

Udemy | English | 13h 24m | 4.21 GB
Created by: Jordan Christman

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