SystemVerilog Functional Coverage for Newbie

SystemVerilog Functional Coverage for Newbie

What you’ll learn

Usage of Functional Coverage in Verification
Implicit and Explicit Bins, Default bins
Illegal bins, Ignore bins, WIldcard bins Default bins
Covergroup, Sampling events, Reusable Covergroup
Transition bins and Cross Coverage
Usage of Functional Coverage in Verilog and SystemVerilog TB
Demonstrations of Functional Coverage with Counters, Priority Encoders, Adders, FIFO, SPI and few other RTL’s

Requirements

Fundamentals of Verilog

Description

The verification process is becoming complex and time-consuming day by day with advances in the Hardware Description Languages and IPs. HDL has added capabilities that allow the engineer to Design and write Testbench for complex systems. But verifying designer intent and deciding set of right stimuli to meet the Verification plan is not always easy with HDL. Hence System Verilog introduces assertions and Coverage to fulfill this requirement by adding independent constructs to language. SystemVerilog assertions allow us to verify Designer intent in both Temporal and Non-Temporal domains. Functional Coverage act like feedback for the stimulus we are sending to DUT so that we could reach to best stimulus for verifying the plan in the least amount of time. This course covers the fundamentals of different types of bins viz, Implicit bins, Explicit bins, Wildcard bins, Ignore bins, default bins, illegal bins with a demonstration of each of them in RTL. Fundamentals of Cover group, Reusable Covergroup, and different Sampling methods viz. event, sample() method, and User-defined Sample Method are discussed in detail. Functional Coverage gives us the ability to verify the relation between the signal by using Cross Coverage and detailed discussion on Cross coverage with different combination filtering strategies are covered in detail. Finally, Transition bins provide temporal abilities to Functional Coverage is also discussed in detail with projects demonstrating the usage of Functional Coverage in Verilog and SystemVerilog Testbench.

Overview

Section 1: Role of Functional Coverage in Chip Design

Lecture 1 Agenda

Lecture 2 Understanding Verification

Lecture 3 Verification Strategies

Lecture 4 Verification Approaches

Lecture 5 Verification Technologies P1

Lecture 6 Verification Technologies P2

Section 2: IDE and Motivation

Lecture 7 Agenda

Lecture 8 Motivation 1 : Knowing how many random values are required to meet Verification

Lecture 9 Motivation 2 : Knowing all the Transitions are Covered by SPI

Lecture 10 Motivation 3: All the possible combinations are tested during Verification

Lecture 11 How to use IDE

Lecture 12 Code

Lecture 13 Course Framework

Section 3: Getting Started

Lecture 14 Agenda

Lecture 15 Fundamentals

Lecture 16 Covergroup without event

Lecture 17 Code

Lecture 18 Covergroup with event

Lecture 19 Code

Lecture 20 Understanding Covergroup options part 1

Lecture 21 Understanding Covergroup options part 2

Lecture 22 Code

Lecture 23 Understanding weight

Lecture 24 Code

Lecture 25 Understanding option and type_option

Lecture 26 Code

Lecture 27 Turning on / off Coverage with specific conditons

Lecture 28 Code

Section 4: Getting started with bins

Lecture 29 Agenda

Lecture 30 Fundamentals of Implicit / automatic bins

Lecture 31 Demonstration

Lecture 32 Code

Lecture 33 Explicit bins P1

Lecture 34 Code

Lecture 35 Explicit bins P2

Lecture 36 Code

Lecture 37 Summary : ways to add values to explicit bins

Lecture 38 default bins

Lecture 39 Code

Lecture 40 Summary : Types of bins

Lecture 41 Used Case : 4:1 Mux

Lecture 42 Code

Lecture 43 Working with enum

Lecture 44 Code

Lecture 45 Used Case : Working with Simple FSM in Verilog

Lecture 46 Code

Lecture 47 Used Case : Working with Simple FSM in SystemVerilog

Lecture 48 Code

Section 5: bins Filtering

Lecture 49 Agenda

Lecture 50 Fundamentals

Lecture 51 bins filtering : with p1

Lecture 52 Code

Lecture 53 bins filtering : with p2

Lecture 54 Code

Lecture 55 Understanding Illegal_bins

Lecture 56 Code

Lecture 57 Understanding Ignore bins

Lecture 58 Code

Lecture 59 Advantages of ignore_bins

Lecture 60 Code

Lecture 61 Ignoring range of values from Coverage

Lecture 62 Code

Lecture 63 Ignore vs Illegal bins

Lecture 64 Code

Lecture 65 Empty bins

Lecture 66 Code

Lecture 67 Wildcard bins

Lecture 68 Code

Lecture 69 Handling presence of ‘X’ or ‘Z’ in Values

Lecture 70 Code

Lecture 71 Used Case

Lecture 72 Code

Lecture 73 FAQ 1

Section 6: Reusable Covergroup

Lecture 74 Agenda

Lecture 75 Fundamentals

Lecture 76 Pass by reference

Lecture 77 Code

Lecture 78 Pass by Value

Lecture 79 Code

Lecture 80 Things to remember while working with Generic Covergroup

Lecture 81 Code

Lecture 82 Used Case I

Lecture 83 Code

Lecture 84 Used Case II

Lecture 85 Code

Section 7: Sample Methods

Lecture 86 Agenda

Lecture 87 Fundamentals

Lecture 88 Method 1: Sampling Event with covergroup

Lecture 89 Code

Lecture 90 Method 2 : Using Pre-build sample() method

Lecture 91 Code

Lecture 92 User define Sample Method inside task block

Lecture 93 User define Sample Method inside function block

Lecture 94 Code

Lecture 95 User defined Sample method inside Property block

Lecture 96 Code

Lecture 97 Summary

Section 8: Cross Coverage

Lecture 98 Agenda

Lecture 99 Understanding Cross Coverage

Lecture 100 Demonstration P1

Lecture 101 Demonstration P2

Lecture 102 Code

Lecture 103 Filtering Combination Method 1: Creating Independent Covergroup

Lecture 104 Code

Lecture 105 Filtering Combination Method 2 : binsof(SIG) intersec {VAL}

Lecture 106 Code 1

Lecture 107 Example 2

Lecture 108 Code 2

Lecture 109 Example 3

Lecture 110 Code

Section 9: Transition bins

Lecture 111 Agenda

Lecture 112 Simple Transition Coverage P1

Lecture 113 Simple Transition Coverage P2

Lecture 114 Code

Lecture 115 Consecutive Repetition Transition

Lecture 116 Code

Lecture 117 Non-Consecutive Transition

Lecture 118 Code

Lecture 119 Summary

Section 10: Projects

Lecture 120 Agenda

Lecture 121 8:1 Mux P1

Lecture 122 8:1 Mux P2

Lecture 123 8:1 Mux P3

Lecture 124 Code

Lecture 125 Priority Encoder : Verilog TB

Lecture 126 Code

Lecture 127 FIFO P1

Lecture 128 FIFO P2

Lecture 129 FIFO P3

Lecture 130 Code

Lecture 131 Usage of Transition bins : Serial Peripheral Interface

Lecture 132 Code

Lecture 133 Counter P1

Lecture 134 Counter P2

Lecture 135 Counter P3

Lecture 136 Code

Anyone interested in adopting Functional Coverage in the Verification process to generate Stimulus meeting Verification plans

Course Information:

Udemy | English | 7h 43m | 1.98 GB
Created by: Kumar Khandagle

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