UVM for Verification Part 1 Fundamentals
What you’ll learn
Fundamentals of Universal Verification Methodology
Reporting Macros and associated actions
UVM Object and UVM Component
UVM Phases
TLM Communication
Sequences
UVM Debugging features
Building UVM Verification Environment from Scratch
Requirements
Fundamentals of SystemVerilog Testbench Environment
Description
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the Verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.The course will discuss the fundamentals of the Universal Verification Methodology. This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test. Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM.
Overview
Section 1: How to use IDE
Lecture 1 Series Intro
Lecture 2 Agenda
Lecture 3 Use this code for understanding IDE’s
Lecture 4 EDAplayground Link
Lecture 5 Working with EDAP
Lecture 6 Working with Vivado
Lecture 7 Working with Questa
Section 2: Reporting Mechanism
Lecture 8 Agenda
Lecture 9 Different Reporting Macros
Lecture 10 Working with Reporting Macros
Lecture 11 Code
Lecture 12 Priniting Values of Variables without automation
Lecture 13 Code
Lecture 14 Working with Verbosity Level
Lecture 15 Code
Lecture 16 Working with Verbosity Level and ID
Lecture 17 Code
Lecture 18 Working with Individual Component
Lecture 19 Code
Lecture 20 Working with Hierarchy
Lecture 21 Code
Lecture 22 Other Reporting Macros
Lecture 23 Code
Lecture 24 Changing Severity of Macros
Lecture 25 Code
Lecture 26 Changing Associated Actions of Macros
Lecture 27 Working with quit_count and UVM_ERROR
Lecture 28 Code
Lecture 29 Working with log file
Lecture 30 Code
Section 3: Getting Started with Base Classes : UVM_OBJECT
Lecture 31 Agenda
Lecture 32 Fundamentals P1
Lecture 33 Fundamentals P2
Lecture 34 Fundamentals P3
Lecture 35 Target
Lecture 36 Creating Class
Lecture 37 Deriving class from UVM_OBJECT
Lecture 38 Using Field Macros P1 : INT cont
Lecture 39 Code
Lecture 40 Using Field Macros P1 : INT
Lecture 41 Code
Lecture 42 Using Field Macros P2 : ENUM, REAL
Lecture 43 Code
Lecture 44 Using Field Macros P3 : OBJECT
Lecture 45 Code
Lecture 46 Using Field Macros P4 : Arrays
Lecture 47 Code
Lecture 48 Copy and Clone Method
Lecture 49 Code
Lecture 50 Shallow Vs Deep Copy
Lecture 51 Code
Lecture 52 Copy and Clone Method
Lecture 53 Code
Lecture 54 Compare Method
Lecture 55 Code
Lecture 56 Create Method
Lecture 57 Code
Lecture 58 Factory Override : new vs create method
Lecture 59 Code
Lecture 60 do_print Method
Lecture 61 Code
Lecture 62 convert2string method
Lecture 63 Code
Lecture 64 do_copy method
Lecture 65 Code
Lecture 66 do_compare
Lecture 67 Building Transaction Class : p
Section 4: UVM_COMPONENT
Lecture 68 Agenda
Lecture 69 Understanding UVM_TREE
Lecture 70 Creating UVM_COMPONENT class
Lecture 71 Code
Lecture 72 Creating UVM_TREE P1
Lecture 73 Creating UVM_TREE P2
Lecture 74 Code
Lecture 75 Getting path of the component : p
Section 5: config_db
Lecture 76 Agenda
Lecture 77 Understanding typical format of config_db
Lecture 78 Code
Lecture 79 Demonstration P1
Lecture 80 Demonstration P2
Lecture 81 Demonstration P3
Lecture 82 Demonstration P4
Lecture 83 Used Case
Lecture 84 Code
Section 6: UVM_PHASES
Lecture 85 Agenda
Lecture 86 Fundamentals of Phases
Lecture 87 Classification of Phases : Methods Used
Lecture 88 Classification of Phases : Specific Purposes P1
Lecture 89 Classification of Phases : Specific Purposes P2
Lecture 90 Classification of Phases : Specific Purposes P3
Lecture 91 Classification Summary
Lecture 92 How we override phases
Lecture 93 Code
Lecture 94 Understanding execuction of build_phase in multiple components
Lecture 95 Code
Lecture 96 Understanding execution of connect_phase
Lecture 97 Code
Lecture 98 Execution of Multiple instance phases
Lecture 99 Raising Objection
Lecture 100 Code
Lecture 101 How Time consuming phases works in Single Component
Lecture 102 Code
Lecture 103 Time Consuming phases in multiple components
Lecture 104 Code
Lecture 105 Timeout
Lecture 106 Code
Lecture 107 Drain Time : Individual Component
Lecture 108 Code
Lecture 109 Drain Time : Multiple Components
Lecture 110 Code
Lecture 111 Phase Debug
Lecture 112 Phase Debug Switch
Lecture 113 Objection Debug
Lecture 114 Objection Debug Switch
Section 7: TLM
Lecture 115 Agenda
Lecture 116 Fundamentals
Lecture 117 Blocking PUT Operation P1
Lecture 118 Code
Lecture 119 Adding IMP to Blocking PUT Operation
Lecture 120 Code
Lecture 121 Port to IMP
Lecture 122 Code
Lecture 123 PORT-PORT to IMP
Lecture 124 Code
Lecture 125 Port to Export-IMP
Lecture 126 Code
Lecture 127 Get Operation
Lecture 128 Code
Lecture 129 Transport Port
Lecture 130 Code
Lecture 131 Analysis Port
Lecture 132 Code
Section 8: Sequence
Lecture 133 Agenda
Lecture 134 Fundamentals
Lecture 135 Creating Sequences
Lecture 136 Code
Lecture 137 Understanding Flow
Lecture 138 Code
Lecture 139 Sending Data to Sequencer
Lecture 140 Code
Lecture 141 Sending Data to Driver Method 2 P1
Lecture 142 Sending Data to Driver Method 2 P2
Lecture 143 Code
Lecture 144 Multiple Sequence in Parallel
Lecture 145 Code
Lecture 146 Changing Arbitration Mechanism P1
Lecture 147 Changing Arbitration Mechanism P2
Lecture 148 Code
Lecture 149 Ways to Hold access of Sequencer
Lecture 150 Holding Access of Sequencer P1
Lecture 151 Code
Lecture 152 Holding access of Sequencer P2 : Priority
Lecture 153 Code
Lecture 154 Holding access of Sequencer P3 : Lock Method
Lecture 155 Code
Lecture 156 Holding access of Sequencer P4 : Grab Method
Lecture 157 Code
Section 9: Projects : Combinational Adder
Lecture 158 Agenda
Lecture 159 Summary of the Verification Environment
Lecture 160 Verification of Combinational adder : DUT
Lecture 161 Transaction Class
Lecture 162 Sequence Class
Lecture 163 Driver Class
Lecture 164 Monitor Class
Lecture 165 Scoreboard Class
Lecture 166 Agent Class
Lecture 167 Environment Class
Lecture 168 Test Class
Lecture 169 Testbench Top
Lecture 170 DUT + Interface
Lecture 171 Testbench
Section 10: Projects : Verification of Sequential Adder
Lecture 172 Design + Interface
Lecture 173 Transaction + Generator
Lecture 174 Driver
Lecture 175 Monitor + Scoreboard
Lecture 176 Agent + ENV + TEST
Lecture 177 Testbench Top
Lecture 178 DUT + Interface
Lecture 179 Testbench
Section 11: Next Course of UVM Series
Lecture 180 UVM for Verification Part 2 : Projects
Anyone interested in Verification Engineer Role
Course Information:
Udemy | English | 10h 51m | 4.38 GB
Created by: Kumar Khandagle
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