UVM for Verification Part 2 Projects

UVM for Verification Part 2 Projects

What you’ll learn

Verification of Combinational Circuits
Verification of Sequential Circuits
Verification of Common Bus Protocols viz. APB, AXI
Verification of Communication Protocols viz. UART, SPI, I2C
Understanding usage of Virtual Sequencer, Sequence Library and TLM analysis FIFO

Requirements

Basic understanding of UVM

Description

Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.This is a Lab-based course designed such that anyone with the fundamentals of UVM could understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGA.  The course covers verification of the combinational circuit like combinational adder, Sequential circuit like Data flip-flop, communication interfaces like a clock generator, UART, SPI, and I2C, and Bus protocols like APB, AXI, and demonstration of few useful UVM concepts like a virtual sequencer, TLM analysis FIFO, and a sequence library.

Overview

Section 1: Agenda

Lecture 1 Course Overview

Section 2: Verification of Combinational Circuit : 4-bit Multiplier

Lecture 2 Multiplier P1

Lecture 3 Multiplier P2

Lecture 4 Multiplier P3

Lecture 5 Design Code

Lecture 6 Verification Environment

Section 3: Verification of Sequential Circuit : Data Flipflop

Lecture 7 DFF P1

Lecture 8 DFF P1

Lecture 9 DFF P3

Lecture 10 Design Code

Lecture 11 Verification Code

Section 4: Verification of UART

Lecture 12 Clock Generator for different Baud

Lecture 13 Verification P1

Lecture 14 Verification P2

Lecture 15 Clock Generator : Design

Lecture 16 Clock Generator : Verification environment

Lecture 17 Understanding UART system

Lecture 18 UART Clock Generator

Lecture 19 UART Transmitter

Lecture 20 UART Receiver

Lecture 21 System Top

Lecture 22 Typical Transaction

Lecture 23 Simple TB code

Lecture 24 Verification Environment P1

Lecture 25 Verification Environment P2

Lecture 26 Design Code

Lecture 27 Verification Environment

Section 5: Verification of SPI Memory

Lecture 28 Understanding SPI Controller RTL

Lecture 29 Understanding SPI Memory

Lecture 30 Typical Transactions

Lecture 31 SPI controller P1

Lecture 32 SPI controller P2

Lecture 33 Design Code

Lecture 34 Verification Environment

Lecture 35 Understanding Native Transactions

Lecture 36 Native SPI P1

Lecture 37 Native SPI P2

Lecture 38 Design Code : Native

Lecture 39 Verification Environment : Native

Section 6: Verification of I2C Memory

Lecture 40 Understanding I2C

Lecture 41 I2C Slave Memory

Lecture 42 I2C Master Controller

Lecture 43 Typical Transaction to DUT

Lecture 44 Verification Environment P1

Lecture 45 Verification Environment P2

Lecture 46 Design Code

Lecture 47 Verification Environment

Section 7: Veriicantion of APB_RAM

Lecture 48 Fundamentals

Lecture 49 Understanding Design

Lecture 50 Understanding Transactions

Lecture 51 ABP_RAM P1

Lecture 52 ABP_RAM P2

Lecture 53 ABP_RAM P3

Lecture 54 Design Code

Lecture 55 Verification Environment

Section 8: Verification of AXI Memory

Lecture 56 Understanding AXI Channels

Lecture 57 Write address Channel

Lecture 58 Write Data Channel

Lecture 59 Write Response Channel

Lecture 60 Single Write Transaction

Lecture 61 Implementing Write Channel P1

Lecture 62 Understanding Burst Type P1

Lecture 63 Understanding Burst Type P2

Lecture 64 Understanding Burst Type P3

Lecture 65 Implementing Write Data Channel

Lecture 66 Implementing Write Response Channel

Lecture 67 Read Channel

Lecture 68 Implementing Read Channel

Lecture 69 Verification Environment P1

Lecture 70 Verification Environment P2

Lecture 71 Verification Environment P3

Lecture 72 Design Code

Lecture 73 Verification Environment

Section 9: Understanding usage of Sequence Library

Lecture 74 Sequence Library P1

Lecture 75 Sequence Library P2

Lecture 76 Code

Section 10: Understanding TLM Analysis FIFO

Lecture 77 Understanding TLM FIFO usage

Lecture 78 Demonstration

Lecture 79 Code

Lecture 80 Usage of TLM Analysis FIFO P1 : Design

Lecture 81 Usage of TLM Analysis FIFO P1 : Verification Env P1

Lecture 82 Usage of TLM Analysis FIFO P1 : Verification Env P2

Lecture 83 Usage of TLM Analysis FIFO P1 : Verification Env P3

Lecture 84 Design Code

Lecture 85 Verification Environment

Section 11: Understanding Virtual Sequencer

Lecture 86 Virtual Sequencer P1

Lecture 87 Virtual Sequencer P2

Lecture 88 DUT

Lecture 89 Verification Environment P1

Lecture 90 Verification Environment P2

Lecture 91 Verification Environment P3

Lecture 92 Design Code

Lecture 93 Verification Environment

Section 12: Next Course of UVM Series

Lecture 94 UVM for Verification Part 3 : UVM RAL

Engineers involved/interested in the verification of RTL’s

Course Information:

Udemy | English | 8h 42m | 3.46 GB
Created by: Kumar Khandagle

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