VHDL for an FPGA Engineer with Vivado Design Suite
What you’ll learn
Fundamentals of VHDL Programming that will help to ace RTL Engineer Job Interviews.
Understand Vivado Design Suite flow for Digital System Design.
How to write an RTL for Synthesis
Different Modelling Styles in Hardware Description Language , Concurrent and Sequential Statements in VHDL
How to use Xilinx IP’s and create Custom IP’s.
IP integrator Design flow of the Vivado.
Writing VHDL Test benches.
Hardware Debugging in Vivado viz. Integrated Logic Analyzer, Virtual I/O.
From Zero to Hero in VHDL
Requirements
Fundamental of Digital Circuit will give an added advantages.
Description
FPGA’s are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic. The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.
Overview
Section 1: Installing Vivado
Lecture 1 Agenda
Lecture 2 How to Download, Install Vivado Design suite and add License.
Lecture 3 Xilinx Vivado Webpack LIC FILE
Lecture 4 How to verify License Installation
Lecture 5 Adding boards such as Nexys 4 DDR which are not available in the Vivado
Lecture 6 Common Error with Vivado: Incorrect Microsoft Visual C++ redistributable package
Section 2: Performance Comparison ( Motivation)
Lecture 7 Agenda
Lecture 8 Demonstration of Parallel architecture usage
Lecture 9 Ease of working with FPGA’s
Lecture 10 User Programmable I/O of FPGA vs MCU
Lecture 11 Comparing Temporary storage
Lecture 12 Whether Coding Guidlines really matters?
Lecture 13 How to buy FPGA board in India (without paying Custom duty and GSTN no.)
Section 3: Frequently Asked Questions
Lecture 14 Q1
Section 4: Vivado Design Flow P1
Lecture 15 Agenda
Lecture 16 Design Flow P1
Lecture 17 Design Flow P2
Lecture 18 Design Flow P3
Lecture 19 Design flow P4
Lecture 20 Design Flow P5
Lecture 21 Summary of Design Flow
Lecture 22 First Look at VHDL Code
Lecture 23 Insights P1
Lecture 24 Insights P2
Lecture 25 Use of RTL analysis
Lecture 26 Use of Post-Synthesis View
Section 5: Vivado Design Flow Part 2
Lecture 27 Agenda
Lecture 28 Understanding I/O Planning Project
Lecture 29 Understanding Synthesis Settings
Lecture 30 Clock Gating
Lecture 31 Fundamentals of FSM Encoding
Lecture 32 Vivado default Synthesis Configuration
Lecture 33 FSM Encoding Technique
Lecture 34 Understanding Implementation Strategies of VIVADO
Lecture 35 Code
Lecture 36 Complete FPGA Design Flow P1
Lecture 37 Complete Design flow P2
Lecture 38 Code
Section 6: Fundamentals : Signal and Variable
Lecture 39 Agenda
Lecture 40 Fundamentals Signal and Variable P1
Lecture 41 Fundamentals Signal and Variable P2
Lecture 42 Format of Signal and Variable
Lecture 43 Datatypes in VHDL
Lecture 44 Using Built-in datatype
Lecture 45 Using Non-builtin datatypes
Lecture 46 Using User defined datatypes
Lecture 47 Using Signal
Lecture 48 Using Variable
Lecture 49 Initialization of Variable
Section 7: Dataflow Modeling Style
Lecture 50 Agenda
Lecture 51 Different Modeling Style
Lecture 52 Dataflow Modeling Style Fundamentals
Lecture 53 Operators in Dataflow Modeling Style
Lecture 54 Assignment Operator in Dataflow Modeling Style
Lecture 55 Implementation of Half adder
Lecture 56 Implementation of Full adder
Lecture 57 Handling Multibit vectors P1
Lecture 58 Handling Multibit vectors P2
Lecture 59 Shift Operators Fundamentals
Lecture 60 Shift Operator Demonstration
Lecture 61 Rotation Operator Fundamentals
Lecture 62 Rotation Operator Demonstration
Lecture 63 Arithmetic Operator Fundamentals
Lecture 64 Arithmetic Opertation : Unsigned Type
Lecture 65 Arithmetic Opertation : Std_logic_Vector Type
Lecture 66 Understanding type-conversion function
Lecture 67 type-conversion Demonstration
Lecture 68 Conditional and Selected Signal Statement
Lecture 69 Conditional and Selected Signal Statement
Section 8: Behavioral Modeling Style
Lecture 70 Agenda
Lecture 71 Understanding Process block
Lecture 72 Behavioral Modeling Style Skeleton
Lecture 73 Understanding IF ELSE P1
Lecture 74 Understanding IF ELSE P2
Lecture 75 Good Practices : IF ELSE P1
Lecture 76 Good Practices : IF ELSE P2
Lecture 77 D-Flipflop with Synchronus Reset
Lecture 78 D-Flipflop with Asynchronus Reset
Lecture 79 Simulation : Asynchronus Reset D-Flipflop
Lecture 80 Simulation : Synchronus Reset D-Flipflop
Lecture 81 Case Statement Skeleton
Lecture 82 4:1 Mux with Case Statement
Lecture 83 Binary to Seven Segment Decoder P1
Lecture 84 Binary to Seven Segment Decoder P2
Lecture 85 Binary to Seven Segment Decoder P3
Lecture 86 Implementing Counter
Lecture 87 Code
Lecture 88 Right Circular Shifter P1
Lecture 89 Right Circular Shifter P2
Lecture 90 Code
Section 9: Understanding Testbench
Lecture 91 Ways to create Testbenches
Lecture 92 Using Force Constant and Force Clock
Lecture 93 VHDL TB Fundamentals P1 : Testbench Overview
Lecture 94 VHDL TB Fundamentals P2 : Generating Random signals
Lecture 95 Code
Lecture 96 VHDL TB Fundamentals P3 : Generating Clock Signal
Lecture 97 Code
Lecture 98 Summary
Lecture 99 Code
Lecture 100 Example 1 : 4-bit Counter
Lecture 101 Code
Lecture 102 Example 2: Adder IP
Section 10: Structural Modeling Style
Lecture 103 Target
Lecture 104 Half adder
Lecture 105 Full adder with Half adder
Lecture 106 Code
Lecture 107 Using Vivado IP Integrator : 4-bit Ripple Carry adder
Lecture 108 Block Design
Lecture 109 Johnson Counter with D FlipFlop
Section 11: Finite State Machines in VHDL
Lecture 110 Target
Lecture 111 State Machines
Lecture 112 Mealy FSM : Three Process Methodolgy
Lecture 113 Code
Lecture 114 Mealy FSM : Two Process Methodology
Lecture 115 Code
Lecture 116 Mealy FSM : SIngle Process Methodology
Lecture 117 Code
Lecture 118 Moore FSM : Three Process Methodology
Lecture 119 Code
Lecture 120 Moore FSM : Two Process Methodology
Lecture 121 Code
Lecture 122 Moore FSM : Single Process Methodology
Lecture 123 Code
Lecture 124 Understanding Sequence Detector
Lecture 125 Implementing Overlapping Sequence Detector
Lecture 126 Code
Lecture 127 Traffic Light Controller Flowchart
Lecture 128 Understanding Traffic Light Controller
Lecture 129 Code
Section 12: Commonly Asked Question’s from previous Module
Lecture 130 What are alternatives to generate stimulis for Sequence detector ? ( Bishal )
Lecture 131 Code
Section 13: Use of IP’s
Lecture 132 Target
Lecture 133 How we Create IP
Lecture 134 How we refresh IP repository
Lecture 135 How we add Customization Parameters to IP
Lecture 136 Complete Design P1 : Barrel Shifter
Lecture 137 Complete Design P2
Section 14: Hardware Debugging
Lecture 138 Undertanding ILA and VIO
Lecture 139 Adding ILA core to design
Lecture 140 Code
Lecture 141 Analyzing Waveform with ILA
Lecture 142 Adding Virtual I/O core to the design
Lecture 143 Code
Lecture 144 Analyzing response of the System with VIO
Section 15: Memories in FPGA
Lecture 145 Understanding Memories in FPGA
Lecture 146 Distributed Memory Vs Block Memory
Lecture 147 Max. Distributed and Block Memory Size
Lecture 148 Creating Memory Method 1
Lecture 149 Creating Memory Method 2
Lecture 150 Creating Memory Method 3
Lecture 151 Single Port RAM with Block Memory
Lecture 152 Single Port RAM with Block Memory
Lecture 153 Single Port RAM with Distributed Memory
Lecture 154 Single Port RAM with Distributed Memory
Lecture 155 Single Port ROM IP with Block Memory and COE file
Lecture 156 Signle Port RAM in VHDL with Testbench
Section 16: Projects
Lecture 157 Project Categories
Section 17: Timing Domain Projects
Lecture 158 Implementation of VGA Controller in VHDL
Lecture 159 Source Code
Section 18: Data dominant Projects
Lecture 160 P1 : Implementing 4-bit Barrel Shifter with Rotate Logic
Lecture 161 System Implementation : 4-bit Barrel Shifter
Lecture 162 P2 : Implementation of Universal Serial Asynchronus Transmitter(UART) with VHDL
Lecture 163 Flowchart and Code
Lecture 164 Implementation of SPI for DAC PMOD DA4 in VHDL
Lecture 165 Code
Lecture 166 Implementing Parallel Interface for Interfacing LCD with FPGA
Section 19: Fundamental of FPGA architecture
Lecture 167 Need of Reprogrammable architecture
Lecture 168 PLD Classification
Lecture 169 Understanding Programmable Logic in PROM
Lecture 170 PROM Demonstration on NI Multisim IDE
Lecture 171 PAL and PLA
Lecture 172 SPLD and GAL
Lecture 173 Understanding GAL Datasheet : 16V8
Lecture 174 SPLD and GAL Summary
Lecture 175 CPLD architecture
Lecture 176 Introduction to FPGA Architecture
Lecture 177 Use of Wide Multiplexer
Lecture 178 Spartan 6 Architecture
Lecture 179 Spartan 6 FPGA Architecture Summary
VLSI Job Seeker/ Graduate student looking to pursue career as RTL Engineer/ Design Engineer/ Verification Engineer.,Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ VHDL Hardware Description Language,Anyone interested to start career in ASIC/ VLSI domain.
Course Information:
Udemy | English | 19h 42m | 6.16 GB
Created by: Kumar Khandagle
You Can See More Courses in the IT & Software >> Greetings from CourseDown.com